1. Field of the Invention
The present invention relates to a method and circuit for controlling timings of display devices using a single data enable signal, and more particularly, to a method and circuit for controlling timings in the porch period of display devices using a single data enable signal.
2. Description of the Prior Art
Display systems can receive image frames contained in video signals via transmission channels. After signal processing, static or dynamic images can be displayed on a screen. Display systems normally adopt GTF (Generalized Timing Formula) standard proposed by VESA (Video Electronics Standards Association), and can be categorized into analog or digital display systems based on the formats of image data.
Traditional cathode ray tube (CRT) devices are analog display systems which operate based on the vision persistence perceived by human eyes. In CRT devices, the image data of an entire frame is not displayed simultaneously on the screen. Instead, image signals are segmented and then scanned sequentially. The first scan starts from one end of a horizontal line to the other end, followed by the second scan starting from one end of the next horizontal line to the other end, and similar operations continue for subsequent scans. In the timing control of the CRT device, a frame signal includes horizontal signals and vertical signals. The horizontal signals include the data signal of each horizontal line, the front porch signal, the horizontal synchronization signal and the back porch signal. The front porch and back porch signals do not carry any data and can provide the CRT device with sufficient time when moving between the start points of different scans. Similarly, the vertical signals include the front porch signal, the vertical synchronization signal and the back porch signal, and provide the same functions as the horizontal signals.
Liquid crystal display (LCD) devices are digital systems characterized in low radiation, small size and low power consumption. Therefore, LCD devices have gradually replaced traditional CRT devices, and are widely used in various electronic products, such as laptop computers, personal digital assistants (PDAs), flat-panel TVs, or mobile phones. In an LCD device, a gate driver transmits scan signals to the scan lines of the display panel for controlling the switches of each pixel, while a source driver transmits image data (such as red, green and blue signals) to the data lines of the display panel for driving the pixels. Due to different structures, the CRT device requires sufficient time for moving the CRT to the correct locations, while the LCD device needs to control the switch turn-on time and the delay of data transmission. Normally, the LCD devices also follow VESA standards when performing internal image-processing and timing control. For example, the horizontal synchronization signal is used for identifying the start points of each horizontal line, while the vertical synchronization signal is used for identifying the start points of each frame.
FIG. 1 is a timing diagram illustrating a prior art method for controlling timings of an LCD device. FIG. 1 shows a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a pixel signal PX. In the display period TD of the LCD device, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync and the data enable signal DE remain at high voltage level, and image data can be written into corresponding pixels. In the porch period TP of the LCD device, the data enable signal DE remains at low voltage level, and no image data is written into the pixels. Meanwhile, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are used for controlling the synchronization between other control signals in the porch period TP.
FIG. 2 is a timing diagram illustrating another prior art method for controlling timings of an LCD device. FIG. 2 shows a data enable signal DE, a pixel data signal PX, and a count value LC. The method illustrated in FIG. 2 can be applied to LCD devices in which no external vertical synchronization signal Vsync nor horizontal synchronization signal Hsync is applied during the porch period TP. Without Vsync and Hsync, this prior art method controls timings in the porch period TP using a single data enable signal DE. At the rising edge of the data enable signal DE, the value of a line counter is reset after timing information is recorded so that the LCD device can perform other functions during the porch period TP based on the recorded count value. However, when the LCD device exits the porch period TP and re-enters the display period TD, deviations (as indicated by Δt in FIG. 1) may occur to the data enable signal DE, thereby affecting the synchronization between the data enable signal DE and internal frames.